distributed arithmetic

This paper discusses a method to design the FIR filter on FPGA, on the basis of distributed arithmetic, by using ROM based LUT.

本文提出了一种采用现场可编程门阵列器件FPGA实现FIR字滤波器硬件电路的方案，该方案基于只读存储器ROM查找表的分布式算法。

Aiming at the disadvantages of analog frequency estimation in traditional receiver, this article proposes an algorithm of digital frequency discrimination based on distributed arithmetic.

针对传统接收机中模拟鉴频方法的缺点，提出了一种基于分布式算法的数字鉴频方法。

Study the Distributed Arithmetic thorough.

对分布式算法进行了较为深入的研究。

In order to examine our system framework, we developed a distributed arithmetic, provided the solutions of this arithmetic in J2EE, mobile agent and our AT-DAS.

为了验证系统的有效性和可实现性，我们设计了一个分布式算法，并且在J2EE、移动Agent和我们AT-DAS中分别给出了这个算法的解决方案。

The work is mainly included: ( 1) Study the Distributed Arithmetic ( DA), research the design of FIR digital filter and analyze its shortcomings.

本论文所做的工作如下：1、学习和研究了采用分布式算法实现FIR数字滤波器的设计方法。

Design Research of Improving Distributed Arithmetic Adaptive digital Filter in FPGA

DA自适应数字滤波器在FPGA中实现的改进研究

The thirty-two order filter is worked out using distributed arithmetic algorithm which is simplified by symmetry.

在算法上采用了分布式算法，并利用对称性简化设计，用16阶的设计完成了32阶的滤波器。

Windows function design method of FIR digital filter is introduced, and the parallel distributed arithmetic is used to implement a32 orders FIR digital filter.

阐述了有限冲击响应（FIR）低通滤波器的窗函数设计方法，利用并行分布式算法在现场可编程门阵列上实现了32阶FIR低通滤波器。

A New Distributed Arithmetic for DCT Design

一种分布式运算实现DCT的新方法

By ap-plying the ROM decompose on the OBC technique, we proposed a new distributed arithmetic for DCT design.

将ROM分解技术应用于基于偏移二进制编码技术的分布式DCT实现，得出了一种分布式运算实现DCT变换的新方法。

Not only DDA operates sum of products as quickly as distributed arithmetic, but also provides an effective method to realize coefficient programmable FIR filter.

该算法不仅继承了分布式算法提高乘积和计算速度的优点，还为系数可编程FIR滤波器的实现提供了有效的解决方案。

Comparison between distributed arithmetic architectures of high-order digital filters

高阶数字滤波器分布式算法结构比较

A method of the implement of FIR filter is given out based on the improved distributed arithmetic method to save the FPGA hardware resource.

这种改进的分布式算法把对信号的滤波过程和抽取过程综合到了一起，大大节约了FPGA的硬件资源。

The application of the high order FIR digital filter with FPGA shows that the realizing structure and the tradeoff of distributed arithmetic will affect the processing speed and the hardware cost.

在滤波器实现方面主要以可编程门阵列（FPGA）为目标器件，给出了实现结构对处理速度和硬件资源占用方面的影响及高阶FIR滤波器采用分布式（DA）算法的具体实现方法。

This paper introduces various arithmetic, according to the characteristics of image manipulation and is easy to the target of the hardware realization, based on the distributed arithmetic to realize the FPGA design.

介绍DCT的各种快速算法，根据图象处理的特点和易于硬件实现的目标选择基于分布算法（Distributed Arithmetic-DA）的DCT结构来实现FPGA设计。

Implementation of FIR Digital Filter with FPGA Based on Distributed Arithmetic

基于DA算法的FIR数字滤波器设计及其FPGA实现

Distributed Arithmetic and its Implementation in FPGA

分布式算术及其在FPGA中的实现

One of the techniques is based on distributed arithmetic ( DA) for inner product computation.

其中的一个技术就是基于分布式算法的内积运算。

A Dynamic Distributed Arithmetic ( DDA) is put forword based on the theory of signed distributed arithmetic.

基于有符号数分布式算法原理，提出了动态分布式算法。

This paper argues deeply the main algorithm used in Digital Down Converter design, such as: CORDIC algorithm, CIC filter theory, Half-Band filter theory, Distributed Arithmetic algorithm;

详细讨论了本论文实现的数字下变频系统中主要的几种算法，分别为：CORDIC算法、CIC滤波器、半带滤波器、分布式算法；

Design of a High Speed FIR Filter ASIC Using Distributed Arithmetic

采用分布式算法的高速FIR滤波器ASIC设计

In this thesis, ROM decomposition technology, offset-binary coding technology and symmetric architecture were used to improve the Serial Distributed Arithmetic FIR structure by ROM size reduction.

本文对分布式算术算法进行了深入研究，运用ROM分解技术、偏移二进制编码（OBC）以及线性相位FIR滤波器的对称结构使得ROM规模减小，实现了串行分布式算法结构的改进。

An IP core based-on FPGA for high-efficiency inner-product operation is implemented, in which a distributed arithmetic algorithm was introduced to compute inner-product.

基于现场可编程门阵列器件，采用分布式运算算法，实现了一种面积有效内积运算IP核的设计。

Distributed arithmetic coding which based on the distributed source coding theory uses arithmetic coding as its core process.

分布式算术编码（Distributed Arithmetic Coding，DAC）是基于分布式信源编码的基本理论，使用算术编码作为编解码的核心过程一种编码方法。

Multiplication operation is transformed to look-up table operation and combining with pipelining technology to reduce hardware resources using and improve processing speed, based on distributed arithmetic.

分布式算法设计分数延迟FIR滤波器是将乘法运算转换为查找表操作并结合流水线技术节省硬件资源，提升处理速度。

We adopt a new distributed arithmetic architecture, NEDA, as a fundamental technique of the DCT/ IDCT transform.

该设计采用分布算式结构&NEDA作为DCT变换的核心技术；

Research and Application of a Dynamic Distributed Arithmetic Based on FPGA

基于FPGA的动态分布式算法的研究与应用

This paper gives a solution of the realization of a large scale FIR filter in FPGA by using Distributed Arithmetic.

该文对在FPGA中利用DA算法实现大规模FIR滤波器，提出了具体的实现方案。

Hardware implementation of the color space conversion based on distributed arithmetic

基于分布式算法的色彩空间转换的硬件实现

This paper introduces a theory of Distributed Arithmetic which could realize the multiplication of constant coefficients efficiently, and presents a method of FIR filter design using look up table based on FPGA.

本文介绍了能高效实现固定常数乘法的分布式算法原理，给出了在FPGA中用查找表实现FIR滤波器的算法设计，并以一个16阶低通滤波器为例说明了设计过程。