digital adder

Design and test of a high speed PRNs digital full adder

高速PRNS数母全加器的设计及测试原则

Development of a High Speed Digital Complex Multiply-adder

一种高速数字复数乘加器的研制

Addend and the summand input, and digital and carry the output device is a half adder.

加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。

By analyzing every part of △∑ D/ A converter, it is demonstrated that power consumption is mainly produced by the full-adder and register of digital part.

通过对各个部分的功耗分析表明，电路功耗主要由数字部分的全加器和寄存器产生。

A new PRNs digital full adder algorithm and its implementation scheme

一种新的PRNS数母全加器算法及其实现方案

A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.

数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。